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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MC14LC5447/D Product Preview Calling Line Identification (CLID) Receiver with Ring Detector The MC14LC5447 is a silicon gate HCMOS IC designed to demodulate Bell 202 and V.23 1200-baud FSK asynchronous data. The primary application for this device is in products that will be used to receive and display the calling number, or message waiting indicator sent to subscribers from participating central office facilities of the public switched network. The device also contains a carrier detect circuit and ring detector which may be used to power up the device. Applications for this device include adjunct boxes, answering machines, feature phones, fax machines, and computer interface products. The MC14LC5447 offers the following performance features. * * * * * * * Ring Detector On-Chip Ring Detect Output for MCU Interrupt Power-Down Mode, Less than 1 A Single Supply: + 3.5 to + 6.0 V Pin Selectable Clock Frequencies: 3.68 MHz, 3.58 MHz, or 455 kHz Two Stage Power-Up for Power Management Control Demodulates Bell 202 and V.23 MC14LC5447 16 1 P SUFFIX PLASTIC DIP CASE 648 16 1 DW SUFFIX SOG PACKAGE CASE 751G ORDERING INFORMATION MC14LC5447P MC14LC5447DW Plastic DIP SOG Package PIN ASSIGNMENT TI RI RDI1 RDI2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD DOC DOR CDO RDO CLKSIN OSCin OSCout BLOCK DIAGRAM 1 2 NC RT PWRUP TIP RING - + BPF DEMOD VAG 14 15 DOR DOC CDO VSS NC = NO CONNECTION RDI1 RDI2 RT 3 4 6 RING DETECT CIRCUIT 13 VALID DATA DETECT 12 INTERNAL POWER UP RDO PWRUP 7 CLOCK GEN OSCin OSCout 10 11 CLKSIN 16 9 8 VDD VSS NO CONNECT (5) This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. REV 0 7/96 (c) Motorola, Inc. 1996 MOTOROLA MC14LC5447 1 ABSOLUTE MAXIMUM RATINGS (Voltages referenced to GND, except where noted) Rating DC Supply Voltage Input Voltage, All Pins DC Current Drain Per Pin Power Dissipation Operating Temperature Range Storage Temperature Range Symbol VDD Vin I PD TA Tstg Value - 0.5 to + 6.0 - 0.5 to VDD + 0.5 10 20 0 to + 70 - 40 to + 150 Unit V V mA mW C C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that normal precautions be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the range VSS (Vin or Vout) VDD. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either VSS or VDD). ELECTRICAL CHARACTERISTICS (All polarities referenced to VSS = 0 V, VDD = + 5 V 10%, unless otherwise noted, TA = 0 to + 70C) Parameter DC Supply Voltage Supply Current (All Output Pins Unloaded) (See Figure 1) RT = 0, PWRUP = 1, XTAL = 3.58 MHz Supply Current (All Output Pins Unloaded) (See Figure 1) PWRUP = 0, RT = Don't Care, XTAL = 3.58 MHz Standby Current (All Output Pins Unloaded) (See Figure 1) RT = 1, PWRUP = 1 Input Voltage 0 Level (CLKSIN, OSCin) Input Voltage 1 Level (CLKSIN, OSCin) Output Voltage High: VDD = 5 V (DOR, DOC, OSCout) IOH = 40 A IOH 1 A IOL = 1.6 mA IOL 1 A Input Leakage Current (OSCin, CLKSIN, PWRUP, RT, RDI1, and RDI2) Output Voltage Low: VDD = 5 V (RDO, RT, CDO) IOL = 2.0 mA Input Threshold Voltage Positive Going: VDD = 5 V (RDI1, RT, PWRUP) (See Figure 3) Input Threshold Voltage Negative Going: VDD = 5 V (RDI1, RT, PWRUP) (See Figure 3) RDI2 Threshold TIP/RING Input dc Resistance Iin VOL VT+ VT- RD2VT Rin -- -- 2.5 2.0 1.0 -- -- -- 2.75 2.3 1.1 250 Symbol VDD IDD IDD ISTBY VIL VIH VOH 2.4 4.95 VOL -- -- 0.4 0.05 1 0.4 3.0 2.6 1.2 -- A V V V V k V Min 3.5 -- -- -- -- VDD x 0.7 Typ 5 2.4 4.0 -- -- -- -- Max 6 3 5.5 1 VDD x 0.3 -- -- Unit V mA mA A V V V Output Voltage Low: VDD = 5 V (DOR, DOC, OSCout) ANALOG CHARACTERISTICS (VDD = + 5 V, TA = + 25C, unless otherwise noted, 0 dBm = 0.7746 Vrms @ 600 ) Characteristic Input Sensitivity: TIP and RING (Pins 1 and 2, VDD = + 5 V) Band-Pass Filter (BPF) Frequency Response (Relative to 1700 Hz @ 0 dBm) 60 Hz 500 Hz 2700 Hz 3300 Hz Min - 40 -- -- -- -- -- Typ - 45 - 64 -4 -3 - 34 - 48 Max -- -- -- -- -- -- dBm Unit dBm dB Carrier Detect Sensitivity MC14LC5447 2 MOTOROLA SWITCHING CHARACTERISTICS (VDD = + 5 V, CL = 50 pF, TA = + 25C) Description OSC Startup (CLKSIN = 1; 3.579 MHz XTAL) Power-Up Low to FSK (Setup Time) Carrier Detect Acquisition Time End of Data to Carrier Detect High Symbol tDOSC tSUPD tDAQ tDCH Min -- 15 -- 8 Typ 2 -- 14 -- Max -- -- -- -- Unit ms ms ms ms TIMING DIAGRAM 0.5 SECOND 0.5 SECOND 2 SECONDS RI 0101 1 DATA RT THRESHOLD TO KEEP PART ON RDO tSUPD PWRUP tDAQ CDO tDCH DOC COOKED DATA DOR tDOSC RAW DATA OSC CLOCK 3.58 MHz, 3.6864 MHz, OR 455 kHz MOTOROLA MC14LC5447 3 VDD TI RI RDI1 RDI2 NC RT PWRUP 1 2 3 4 5 6 7 16 0.1 F 15 14 13 12 11 10 9 DOC DOR CDO RDO CLKSIN OSCin OSCout OPEN VDD 8 RT 1 0 X PWRUP 1 1 0 IDD OSCin 1 A MAX DISABLE 2.4 mA TYP ENABLE 6.2 mA TYP ENABLE 3.579 MHz 30 pF 10 M 30 pF Figure 1. IDD Test Circuit PIN DESCRIPTIONS TI Tip Input (Pin 1) This input pin is normally connected to the tip side of the twisted pair. It is internally biased to 1/2 supply voltage when the device is in the power-up mode. This pin must be dc isolated from the line. RI Ring Input (Pin 2) This input is normally connected to the ring side of the twisted pair. It is internally biased to 1/2 supply voltage when the device is in the power-up mode. This pin must be dc isolated from the line. RDI1 Ring Detect Input 1 (Pin 3) This input is normally coupled to one of the twisted pair wires through an attenuating network. It detects energy on the line and enables the oscillator and precision ring detection circuitry. RDI2 Ring Detect Input 2 (Pin 4) This input to the precision ring detection circuit is normally coupled to one of the twisted pair wires through an attenuating network. A valid ring signal as determined from this input sends the RDO (Pin 12) to a logic 0. RT Ring Time (Pin 6) An RC network may be connected to this pin. The RC time constant is chosen to hold this pin voltage below 2.2 V between the peaks of the ringing signal. RT is an internal power-up control and activates only the circuitry necessary to determine if the incoming ring is valid. PWRUP Power Up (Pin 7) A logic 0 on the PWRUP input causes the device to be in the active mode ready to demodulate incoming data. A logic 1 on this pin causes the device to be in the standby mode, if the RT input pin is at a logic 1. This pin may be controlled by RDO and CDO for auto power-up operation. For other applications, this pin may be controlled externally. VSS Ground (Pin 8) Ground return pin is typically connected to the system ground. OSCout Oscillator Output (Pin 9) This pin will have either a crystal or a ceramic resonator tied to it with the other end connected to OSCin. OSCin Oscillator Input (Pin 10) This pin will have either a crystal or a ceramic resonator tied to it with the other end connected to OSCout. OSCin may also be driven directly from an appropriate external source. CLKSIN Clock Select Input (Pin 11) A logic 1 on this input configures the device to accept either a 3.579 MHz or 3.6864 MHz crystal. A logic 0 on this pin configures the part to operate with a 455 kHz resonator. For crystal and resonator specifications see Table 1. RDO Ring Detect Out (Pin 12) This open-drain output goes low when a valid ringing signal is detected. RDO remains low as long as the ringing signal remains valid. This signal can be used for auto power- up, when connected to Pin 7. CDO Carrier Detect Output (Pin 13) When low, this open drain output indicates that a valid carrier is present on the line. CDO remains low as long as the carrier remains valid. An 8 ms hysteresis is built in to allow for a momentary drop out of the carrier. CDO may be used in the auto power-up configuration when connected to PWRUP. MC14LC5447 4 MOTOROLA DOR Data Out Raw (Pin 14) This pin presents the output of the demodulator whenever CDO is low. This data stream includes the alternate 1 and 0 pattern, and the 150 ms of marking, which precedes the data. At all other times, DOR is held high. DOC Data Out Cooked (Pin 15) This output presents the output of the demodulator whenever CDO is low, and when an internal validation sequence has been successfully passed. The output does not include the alternate 1 and 0 pattern. At all other times, DOC is held high. VDD Positive Power Supply (Pin 16) The digital supply pin, which is connected to the positive side of the power supply. APPLICATIONS INFORMATION The MC14LC5447 has been designed to be one of the main functional blocks in products targeted for the CLASS (Custom Local Area Signaling Service) market. CLASS is a set of subscriber features now being presented to the consumer by the RBOCs (Regional Bell Operating Companies) and independent TELCOs. Among CLASS features, such as distinctive ringing and selective call forwarding, the subscriber will also have available a service known as Calling Number Delivery (CND) and message waiting. With these services, a subscriber will have the ability to display at a minimum, a message containing the phone number of the calling party, the date, and the time. A message containing only this information is known as a single format message, as shown in Figure 9. An extended message, known as multiple format message, can contain additional information as shown in Figure 10. The interface should be arranged to allow simplex data transmission from the terminating central office, to the CPE (Customer Premises Equipment), only when the CPE is in an on-hook state. The data will be transmitted in the silent period between the first and second power ring after a voice path has been established. The data signaling interface should conform to Bell 202, which is described as follows: The transmission level from the terminating C.O. will be - 13.5 dBm 1.0. The expected worst case attenuation through the loop is expected to be - 20 dB. The receiver therefore, should have a sensitivity of approximately - 34.5 dBm to handle the worst case installations. Additional information on CLASS services can be obtained from: BELLCORE CUSTOMER SVS. 1-800-521-2673 201-699-5800 FOREIGN CALLS 201-699-0936 FAX The document number is: TA-NWT-000030 Title: "Voice Band Data Transmission Interface Generic Requirements" Figure 7 is a conceptual design of how the MC14LC5447 can be implemented into a product which will retrieve the incoming message and convert it to EIA-232 levels for transmission to the serial port of a PC. With this message and appropriate software, the PC can be used to look up the name and any additional information associated with the caller that had been previously stored. Figure 8 is a conceptual design of an adjunct unit in parallel with an existing phone. This arrangement gives the subscriber CND service without having to replace existing equipment. Table 1. Oscillator Specifications Clock Select Pin 11 = 1 Crystal Mode Frequency Rf C1 and C2 Parallel 3.579 MHz or 3.6864 MHz 10 M 30 pF OSCin OSCout Source: Fox Electronics 5570 Enterprise Pkwy. Ft. Myers, FL 33905 Tel. 813-693-0099 Clock Select Pin 11 = 0 Resonator Frequency Rf C1 and C2 #CSB455J 455 kHz 0.5% 1.0 M 100 pF RF C1 C2 * * * * * Analog, phase coherent, frequency shift keying Logical 1 (Mark) = 1200 12 Hz Logical 0 (Space) = 2200 22 Hz Transmission rate = 1200 bps Application of data = serial, binary, asynchronous Source: Murata Manufacturing Co. Ltd. 2200 Lake Park Dr. Smyma, GA 30080 Tel. 404-436-1300 NOTE: Motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing. MOTOROLA MC14LC5447 5 DESIGN INFORMATION The circuit in Figure 2 illustrates in greater detail the relationship between Pins 3, 4, 6, and 7. The external component values shown in Figure 2 are the same as those shown in Figures 7 and 8. When VDD is applied to the circuit in these two figures, the RC network will charge cap C1 to VDD holding RT (Pin 6) off. If the PWRUP (Pin 7) is also held at VDD, the MC14LC5447 will be in a power-down mode, and will consume 1 A of supply current (max). The resistor network (R2 - R4) attenuates the incoming power ring applied to the top of R2. The values given have been chosen to provide a sufficient voltage at RDI1 (Pin 3) to turn on the Schmitt-trigger input with approximately a 40 Vrms or greater power ring input from tip and ring. When VT+ of the Schmitt is exceeded, Q1 will be driven to saturation discharging cap C1 on RT. This will initialize a partial power-up, with only the portions of the part involved with the ring signal analysis enabled, including RDI2 (Pin 4). At this time the MC14LC5447 power consumption is increased to approximately 2.4 mA (typ). EXTERNAL COMPONENTS 7 PWRUP R1 270 k VDD C1 0.2 F 6 RT Q1 PWRUP LOGIC TO BRIDGE 470 k R2 R3 18 k 4 R4 15 k RDI2 RING ANALYSIS CIRCUIT Vref 1.2 V 3 RDI1 INTERNAL POWER- UP TO RDO PIN INTERNAL COMPONENTS 3.5 3.25 3.0 2.75 VT 2.5 VT+ VT- 2.25 2.0 1.75 1.5 1.25 1.0 2.5 3.0 3.5 4.0 4.5 VDD 5.0 5.5 6.0 6.5 Figure 3. VDD versus VT+ and VT- A ring is qualified when an internal count of binary 48 is reached. The ring is disqualified when the count drops to a binary 32. The number of ring cycles required to qualify the signal will depend on the amplitude of the voltage presented to RDI2. The shortest amount of time needed to do the qualification is approximately 60 ms. The shortest amount of time required for dequalification will be approximately 40 ms. Once the ring signal is qualified, the RDO pin will be sent low. This can be fed back to PWRUP as shown in Figure 7, or with a pull-up resistor, can be used as an interrupt to an MCU as shown in Figure 8. In either case, once the PWRUP pin is below VT-, the part will be fully powered up, and ready to receive FSK. During this mode, the device current will increase to approximately 6.2 mA (typ). The state of the RT pin is now a "don't care" as far as the part is concerned. Normally, however, this pin will be allowed to return to VDD. After the FSK message has been received, the PWRUP pin can be allowed to return to VDD and the part will return to the standby mode, consuming less than 1 A of supply current. The part is now ready to repeat the same sequence for the next incoming message. TYPICAL DEMODULATOR PERFORMANCE The following describes the performance of the MC14LC5447 demodulator in the presence of noise over a simulated Bell 3002 telephone loop. The Bell 3002 loop represents a worst case local telephone loop in North America. The characteristics of this loop, which affect performance, are high frequency attenuation and Envelope Delay Distortion (EDD) or group delay. The minimum receiver sensitivity of the MC14LC5447 under these conditions is typically - 45 dBm. The MC14LC5447 achieves a Bit Error Rate (BER) of 1 x 10-5 at a Signal-to-Noise Ratio (SNR) of 15 dB in V.23 operation and at an SNR of 18 dB in Bell 202 operation (see Figures 4 and 5). All measurements in dBm are referenced to 600 : 0 dBm = 0.7746 Vrms. All measurements were taken using the MC145460EVK evaluation board. Figure 2. The value of R1 and C1 must be chosen to hold the RT pin voltage below the VT+ of the RT Schmitt between the individual cycles of the power ring. The values shown will work for ring frequencies of 15.3 Hz (min). With RDI2 now enabled, a portion of the power ring above 1.2 V is fed to the ring analysis circuit. This circuit is a digital integrator which looks at the duty cycle of the incoming signal. When the input to RDI2 is above 1.2 V, the integrator is counting up at an 800 Hz rate. When the input to RDI2 falls below 1.2 V, the integrator counts down at a 400 Hz rate. MC14LC5447 6 MOTOROLA Electronic file not available for this figure. To view the complete document, order it from the Literature Center. Electronic file not available for this figure. To view the complete document, order it from the Literature Center. Figure 4. MC14LC5447 V.23 Operation (Typical BER vs SNR) Figure 5. MC14LC5447 Bell 202 Operation (Typical BER vs SNR) VDD 500 pF TIP 10 k 500 pF RING 10 k TI RI RDI1 RDI2 N/C VDD RT PWRUP 1 2 3 4 5 6 7 8 16 0.1 f 15 14 13 12 11 10 9 DOC DOR CDO RDO CLKSIN OSCin OSCout VDD 3.579 MHz 30 pF 10 M 30 pF Figure 6. Full-Time Power without Ring Detect MOTOROLA MC14LC5447 7 APPLICATION CIRCUIT 500 pF C1 TIP PROTECTION NETWORK RING C2 1N4004x4 TI 1 RI 2 RDI1 3 RDI2 4 500 pF C4 10 k NC 5 RT 6 PWRUP 7 18 k +5 V 15 k NOTE: C1 and C2 0.2 F required for line isolation. C1 through C4 are 250 V min, non-polarized. +5 V 270 k 8 16 C3 10 k MC14LC5447 VDD 0.1 F 15 DOC 14 DOR 13 CDO 12 RDO 11 CLKSIN 10 OSCin 9 OSCout VDD MC145407 TO PC TO PC 470 k 3.579 MHz 30 pF 10 M 30 pF 4.7 M 0.2 F 0.33 F Figure 7. Partial Implementation of PC Interface to Tip and Ring FIRST RING 2 SECONDS RI 0.5 SEC 0101 1 DATA 0.5 SEC SECOND RING 2 SECONDS RT RDO NOTE 1 NOTE 3 PWRUP NOTE 2 CDO NOTE 1 DOR DATA DOC DATA OSC 3.58 MHz, 3.6864, OR 455 kHz NOTES: 1. Wired `OR' RDO with CDO. 2. Overlap of RDO edge with CDO edge to ensure part stays in PWRUP determined by RC time constant on RDO, PWRUP, and CDO pin. 3. Part reverts to PWR ON, on rising edge of RDO since there is no CDO. Timing Diagram for Figure 7 MC14LC5447 8 MOTOROLA APPLICATION CIRCUIT 0.1 F 500 pF 500 pF C1 TIP 0.2 F C3 C4 10 k 10 k VDD 2 k 2 k TI 1 RI 2 RDI1 3 RDI2 4 NC 5 RT 6 C2 RING 0.2 F 470 k VDD 270 k MCU 0.2 F 3.68 MHz PWRUP 7 8 16 MC14LC5447 15 DOC 14 DOR 13 CDO 12 RDO 11 CLKSIN 10 OSCin 9 OSCout INTERRUPT VDD TO PHONE 18 k 15 k DISPLAY Figure 8. Adjunct Box Concept for Calling Number Display FIRST RING 2 SECONDS RI 0.5 SEC 0101 1 DATA 0.5 SEC SECOND RING 2 SECONDS RT RDO INTERRUPT FOR MCU PWRUP NOTE 1 NOTE 1 NOTE 2 CDO DOC DATA DOR DATA OSC 3.58 MHz, 3.6864 MHz, OR 455 kHz NOTES: 1. MCU must assert PWRUP to MC14LC5447. 2. No data detected, MCU powers down the MC14LC5447. Timing Diagram for Figure 8 MOTOROLA MC14LC5447 9 2s 0.5 s STD RING/20 Hz MESSAGE TYPE WORD 30 BYTES/600 Hz MARKS 01010101 70 250 ms ms 8 8 BITS BITS 495 ms 4s 0.5 s DATA WORD COUNT 2s CHECK SUM DATA 175 ms 144 BITS MAX 8 BITS MO - DAY - HOUR - MINUTE - NUMBER 04 - 15 - 16 - 21 - 512 555 1212 Figure 9. Single Message Format 2s 0.5 s STD RING/20 Hz VARIABLE 4s 0.5 s 2s 250 ms 70 ms VARIABLE DATA DATA CHECK SUM 30 BYTES/600 Hz MARKS 01010101 8 8 8 8 BITS BITS BITS BITS DATA 8 8 BITS BITS 144 DATA BITS 8 BITS MESSAGE TYPE WORD PARAMETER TYPE WORD PARAMETER LENGTH WORD CALLING NAME PARAMETER TYPE WORD MO - DAY - HOUR - MINUTE - NUMBER 04 - 15 - 16 - PARAMETER LENGTH WORD 21 - 512 555 1212 MESSAGE LENGTH WORD Figure 10. Multiple Message Format MC14LC5447 10 MOTOROLA PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP CASE 648-08 -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 B 1 8 F S C L -T- H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M DW SUFFIX SOG PACKAGE CASE 751G-02 -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 -B- 1 8 8X P 0.010 (0.25) M B M 16X D M J TA S 0.010 (0.25) B S F R X 45_ C -T- 14X DIM A B C D F G J K M P R G K SEATING PLANE M MOTOROLA MC14LC5447 11 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MC14LC5447 12 *MC14LC5447/D* MC14LC5447/D MOTOROLA |
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